void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
    for (CacheBlk& blk : blks) {
        visitor(blk);
    }
}

BaseTags::BaseTags(const Params &p)
    : ClockedObject(p), blkSize(p.block_size), blkMask(blkSize - 1),
      size(p.size), lookupLatency(p.tag_latency),
      system(p.system), indexingPolicy(p.indexing_policy),
      warmupBound((p.warmup_percentage/100.0) * (p.size / p.block_size)),
      warmedUp(false), numBlocks(p.size / p.block_size),
      dataBlks(new uint8_t[p.size]), // Allocate data storage in one big chunk
      stats(*this)
{
    // registerExitCallback([this]() { cleanupRefs(); });
    registerExitCallback([this]() { DPRINTF(DumpCache,"%s",print()); });
}

任务1 = A1 A2 B1 C1 D1 A3 A4 D2 C2 B2

任务1A：A1 A2 A3 A4
任务1B：B1 B2
任务1C：C1 C2
任务1D：D1 D2

任务2 = B‘1 A’1 B‘2 C’1 C‘2 D'1 D’2 D‘3 C’3 A‘2
任务2A = A’1 A’2
任务2B = B’1 B’2
任务2C = C’1 C’2 C’3
任务2D = D'1 D’2 D‘3 

PA：A1 A2 A3 A4 A’1 A’2
PB：B1 B2 B’1 B’2
PC：C1 C2 C’1 C’2 C’3
PD：D1 D2 D'1 D’2 D‘3 

class Event : public EventBase, public Serializable {
  Event *nextBin;  // Bin defined as when+priority
  Event *nextInBin;
  Tick _when;    // timestamp when event should be processed
  Priority _priority; //!< event priority
  Flags flags;
  Counter instance;  // event unique ID
  EventQueue *queue;

  static Event *insertBefore(Event *event, Event *curr);
  static Event *removeItem(Event *event, Event *last);

  virtual void process() = 0;
  bool scheduled() const { return flags.isSet(Scheduled); }
  
  // Managed event scheduled and being held in the event queue.
  void acquire() { if (flags.isSet(Event::Managed))  acquireImpl(); }

  // Managed event removed from the event queue.
  void release() { if (flags.isSet(Event::Managed))  releaseImpl(); }
  
  void setWhen(Tick when, EventQueue *q)
}

memcpy(fetchBuffer[tid], pkt->getConstPtr<uint8_t>(), fetchBufferSize);
fetchBufferValid[tid] = true;
。。。
if (checkStall(tid)) {
    fetchStatus[tid] = Blocked;
} else {
    fetchStatus[tid] = IcacheAccessComplete;
}

pkt->req->setAccessLatency();
cpu->ppInstAccessComplete->notify(pkt);

memcpy(dec_ptr->moreBytesPtr(),
        fetchBuffer[tid] + blkOffset * instSize, instSize);
decoder[tid]->moreBytes(this_pc, fetchAddr);

if (dec_ptr->needMoreBytes()) {
    blkOffset++;
    fetchAddr += instSize;
    pcOffset += instSize;
}

renamed_reg = map->lookup(flat_reg);
。。。
inst->renameSrcReg(src_idx, renamed_reg);

rename_result = map->rename(flat_dest_regid);
        inst->renameDestReg(dest_idx,
                            rename_result.first,
                            rename_result.second);

Rename::tick()->Rename::RenameInsts()
IEW::tick()->IEW::dispatchInsts()
IEW::tick()->InstructionQueue::scheduleReadyInsts()
IEW::tick()->IEW::executeInsts()
IEW::tick()->IEW::writebackInsts()
Commit::tick()->Commit::commitInsts()->Commit::commitHead()

IEW::tick()->IEW::executeInsts()
  ->LSQUnit::executeLoad()
    ->StaticInst::initiateAcc()
      ->LSQ::pushRequest()
        ->LSQUnit::read()
          ->LSQRequest::buildPackets()
          ->LSQRequest::sendPacketToCache()
    ->LSQUnit::checkViolation()
DcachePort::recvTimingResp()->LSQRequest::recvTimingResp()
  ->LSQUnit::completeDataAccess()
    ->LSQUnit::writeback()
      ->StaticInst::completeAcc()
      ->IEW::instToCommit()
IEW::tick()->IEW::writebackInsts()

IEW::tick()->IEW::executeInsts()
  ->LSQUnit::executeStore()
    ->StaticInst::initiateAcc()
      ->LSQ::pushRequest()
        ->LSQUnit::write()
    ->LSQUnit::checkViolation()
Commit::tick()->Commit::commitInsts()->Commit::commitHead()
IEW::tick()->LSQUnit::commitStores()
IEW::tick()->LSQUnit::writebackStores()
  ->LSQRequest::buildPackets()
  ->LSQRequest::sendPacketToCache()
  ->LSQUnit::storePostSend()
DcachePort::recvTimingResp()->LSQRequest::recvTimingResp()
  ->LSQUnit::completeDataAccess()
    ->LSQUnit::completeStore()

if (add_to_iq) {
    instQueue.insert(inst);
}
insts_to_dispatch.pop();

DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex());

while (dep_inst) {
    DPRINTF(IQ, "Waking up a dependent instruction, [sn:%llu] "
            "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());

    // Might want to give more information to the instruction
    // so that it knows which of its source registers is
    // ready.  However that would mean that the dependency
    // graph entries would need to hold the src_reg_idx.
    dep_inst->markSrcRegReady();

    addIfReady(dep_inst);

    dep_inst = dependGraph.pop(dest_reg->flatIndex());

    ++dependents;
}

load_fault = inst->initiateAcc();

iew.ldstQueue.pushRequest
Fault
LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
        unsigned int size, Addr addr, Request::Flags flags, uint64_t *res,
        AtomicOpFunctorPtr amo_op, const std::vector<bool>& byte_enable)

request = new SingleDataRequest(&thread[tid], inst, isLoad, addr,
        size, flags, data, res, std::move(amo_op));
        request->initiateTranslation();

Fault
LSQ::read(LSQRequest* request, ssize_t load_idx)
{
    assert(request->req()->contextId() == request->contextId());
    ThreadID tid = cpu->contextToThread(request->req()->contextId());

    return thread.at(tid).read(request, load_idx);
}

case class UpwardParam(width: Int)
case class DownwardParam(width: Int)
case class EdgeParam(width: Int)

object AdderNodeImp extends SimpleNodeImp[DownwardParam, UpwardParam, EdgeParam, UInt] {
  def edge(pd: DownwardParam, pu: UpwardParam, p: Parameters, sourceInfo: SourceInfo) = {
    if (pd.width < pu.width) EdgeParam(pd.width) else EdgeParam(pu.width)
  }
  def bundle(e: EdgeParam) = UInt(e.width.W)
  def render(e: EdgeParam) = RenderedEdge("blue", s"width = ${e.width}")
}

class AdderDriverNode(widths: Seq[DownwardParam])(implicit valName: ValName)
  extends SourceNode(AdderNodeImp)(widths)

/** node for [[AdderMonitor]] (sink) */
class AdderMonitorNode(width: UpwardParam)(implicit valName: ValName)
  extends SinkNode(AdderNodeImp)(Seq(width))

/** node for [[Adder]] (nexus) */
class AdderNode(dFn: Seq[DownwardParam] => DownwardParam,
                uFn: Seq[UpwardParam] => UpwardParam)(implicit valName: ValName)
  extends NexusNode(AdderNodeImp)(dFn, uFn)

class Adder(implicit p: Parameters) extends LazyModule {
  val node = new AdderNode (
    { case dps: Seq[DownwardParam] =>
      require(dps.forall(dp => dp.width == dps.head.width), "inward, downward adder widths must be equivalent")
      dps.head
    },
    { case ups: Seq[UpwardParam] =>
      require(ups.forall(up => up.width == ups.head.width), "outward, upward adder widths must be equivalent")
      ups.head
    }
  )
  lazy val module = new LazyModuleImp(this) {
    require(node.in.size >= 2)
    node.out.head._1 := node.in.unzip._1.reduce(_ + _)
  }

  override lazy val desiredName = "Adder"
}

/** driver (source)
  * drives one random number on multiple outputs */
class AdderDriver(width: Int, numOutputs: Int)(implicit p: Parameters) extends LazyModule {
  val node = new AdderDriverNode(Seq.fill(numOutputs)(DownwardParam(width)))

  lazy val module = new LazyModuleImp(this) {
    // check that node parameters converge after negotiation
    val negotiatedWidths = node.edges.out.map(_.width)
    require(negotiatedWidths.forall(_ == negotiatedWidths.head), "outputs must all have agreed on same width")
    val finalWidth = negotiatedWidths.head

    // generate random addend (notice the use of the negotiated width)
    val randomAddend = FibonacciLFSR.maxPeriod(finalWidth)

    // drive signals
    node.out.foreach { case (addend, _) => addend := randomAddend }
  }

  override lazy val desiredName = "AdderDriver"
}

class AdderMonitor(width: Int, numOperands: Int)(implicit p: Parameters) extends LazyModule {
  val nodeSeq = Seq.fill(numOperands) { new AdderMonitorNode(UpwardParam(width)) }
  val nodeSum = new AdderMonitorNode(UpwardParam(width))

  lazy val module = new LazyModuleImp(this) {
    val io = IO(new Bundle {
      val error = Output(Bool())
    })

    // print operation
    printf(nodeSeq.map(node => p"${node.in.head._1}").reduce(_ + p" + " + _) + p" = ${nodeSum.in.head._1}")

    // basic correctness checking
    io.error := nodeSum.in.head._1 =/= nodeSeq.map(_.in.head._1).reduce(_ + _)
  }

  override lazy val desiredName = "AdderMonitor"
}

class AdderTestHarness()(implicit p: Parameters) extends LazyModule {
  val numOperands = 2
  val adder = LazyModule(new Adder)
  // 8 will be the downward-traveling widths from our drivers
  val drivers = Seq.fill(numOperands) { LazyModule(new AdderDriver(width = 8, numOutputs = 2)) }
  // 4 will be the upward-traveling width from our monitor
  val monitor = LazyModule(new AdderMonitor(width = 4, numOperands = numOperands))

  // create edges via binding operators between nodes in order to define a complete graph
  drivers.foreach{ driver => adder.node := driver.node }

  drivers.zip(monitor.nodeSeq).foreach { case (driver, monitorNode) => monitorNode := driver.node }
  monitor.nodeSum := adder.node

  lazy val module = new LazyModuleImp(this) {
    // when(monitor.module.io.error) {
    //   printf("something went wrong")
    // }
  }

  override lazy val desiredName = "AdderTestHarness"
}

class AXI4MyCLINT(address: Seq[AddressSet])(implicit p: Parameters) extends LazyModule {
  val beatBytes = 4
  val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
    Seq(AXI4SlaveParameters(
        address       = address,
        executable    = true,
        supportsWrite = TransferSizes(1, beatBytes),
        supportsRead  = TransferSizes(1, beatBytes),
        interleavedId = Some(0))
    ),
    beatBytes  = beatBytes)))

  lazy val module = new Impl
  class Impl extends LazyModuleImp(this) {
  }
}

class AXI4MySDRAM(address: Seq[AddressSet])(implicit p: Parameters) extends LazyModule {
  val beatBytes = 4
  val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
    Seq(AXI4SlaveParameters(
        address       = address,
        executable    = true,
        supportsWrite = TransferSizes(1, beatBytes),
        supportsRead  = TransferSizes(1, beatBytes),
        interleavedId = Some(0))
    ),
    beatBytes  = beatBytes)))

  lazy val module = new Impl
  class Impl extends LazyModuleImp(this) {
    val (in, _) = node.in(0)
    val sdram_bundle = IO(new SDRAMIO)

    val msdram = Module(new sdram_top_axi)
    msdram.io.clock := clock
    msdram.io.reset := reset.asBool
    msdram.io.in <> in
    sdram_bundle <> msdram.io.sdram
  }
}

class MySoC(implicit p: Parameters) extends LazyModule {
  val xbar = AXI4Xbar()
  val cpu = LazyModule(new CPU(idBits = ChipLinkParam.idBits))
  val lmrom = LazyModule(new AXI4MROM(AddressSet.misaligned(0x20000000, 0x10000)))
  val lclint = LazyModule(new AXI4MyCLINT(AddressSet.misaligned(0x10000000, 0x10000)))
  val sdramAddressSet = AddressSet.misaligned(0x80000000L, 0x2000000)
  val lsdram_axi = Some(LazyModule(new AXI4MySDRAM(sdramAddressSet))) 

  List(lsdram_axi.get.node ,lmrom.node, lclint.node).map(_ := xbar)
  xbar := cpu.masterNode
  
  override lazy val module = new Impl
  class Impl extends LazyModuleImp(this) with DontTouch {

    cpu.module.reset := SynchronizerShiftReg(reset.asBool, 10) || reset.asBool
    cpu.module.slave := DontCare
    val intr_from_chipSlave = IO(Input(Bool()))
    cpu.module.interrupt := intr_from_chipSlave
    val sdramBundle = lsdram_axi.get.module.sdram_bundle
    val sdram = IO(chiselTypeOf(sdramBundle))
    sdram <> sdramBundle
  }
}

def anoise[T <: AXI4BundleA](bits: T): Unit = {
  bits.id    := LFSRNoiseMaker(bits.params.idBits)
  bits.addr  := LFSRNoiseMaker(bits.params.addrBits)
  bits.len   := LFSRNoiseMaker(bits.params.lenBits)
  bits.size  := LFSRNoiseMaker(bits.params.sizeBits)
  bits.burst := LFSRNoiseMaker(bits.params.burstBits)
  bits.lock  := LFSRNoiseMaker(bits.params.lockBits)
  bits.cache := LFSRNoiseMaker(bits.params.cacheBits)
  bits.prot  := LFSRNoiseMaker(bits.params.protBits)
  bits.qos   := LFSRNoiseMaker(bits.params.qosBits)
}

(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
   val arnoise = Wire(new AXI4BundleAR(edgeIn.bundle))
   val awnoise = Wire(new AXI4BundleAW(edgeIn.bundle))
   val wnoise  = Wire(new  AXI4BundleW(edgeIn.bundle))
   val rnoise  = Wire(new  AXI4BundleR(edgeIn.bundle))
   val bnoise  = Wire(new  AXI4BundleB(edgeIn.bundle))

   arnoise := DontCare
   awnoise := DontCare
   wnoise := DontCare
   rnoise := DontCare
   bnoise := DontCare

   anoise(arnoise)
   anoise(awnoise)

   wnoise.data := LFSRNoiseMaker(wnoise.params.dataBits)
   wnoise.strb := LFSRNoiseMaker(wnoise.params.dataBits/8)
   wnoise.last := LFSRNoiseMaker(1)(0)

   rnoise.id   := LFSRNoiseMaker(rnoise.params.idBits)
   rnoise.data := LFSRNoiseMaker(rnoise.params.dataBits)
   rnoise.resp := LFSRNoiseMaker(rnoise.params.respBits)
   rnoise.last := LFSRNoiseMaker(1)(0)

   bnoise.id   := LFSRNoiseMaker(bnoise.params.idBits)
   bnoise.resp := LFSRNoiseMaker(bnoise.params.respBits)

   feed(out.ar, in.ar, arnoise)
   feed(out.aw, in.aw, awnoise)
   feed(out.w,  in.w,   wnoise)
   feed(in.b,   out.b,  bnoise)
   feed(in.r,   out.r,  rnoise)

val (tl_out, edge_out) = outer.masterNode.out(0)

def out: Seq[(BO, EO)] = {
  require(
    instantiated,
    s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
  )
  bundleOut.zip(edgesOut)
}

abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
  val inner: InwardNodeImp[DI, UI, EI, BI],
  val outer: OutwardNodeImp[DO, UO, EO, BO]
)

abstract class AbstractALU(implicit p: Parameters) extends CoreModule()(p) {
  val io = IO(new Bundle {
    val dw = Input(UInt(SZ_DW.W))
    val fn = Input(UInt(SZ_ALU_FN.W))
    val in2 = Input(UInt(xLen.W))
    val in1 = Input(UInt(xLen.W))
    val out = Output(UInt(xLen.W))
    val adder_out = Output(UInt(xLen.W))
    val cmp_out = Output(Bool())
  })
}

// SLL, SRL, SRA
val (shamt, shin_r) =
  if (xLen == 32) (io.in2(4,0), io.in1)
  else {
    require(xLen == 64)
    val shin_hi_32 = Fill(32, isSub(io.fn) && io.in1(31))
    val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
    val shamt = Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0))
    (shamt, Cat(shin_hi, io.in1(31,0)))
  }
val shin = Mux(shiftReverse(io.fn), Reverse(shin_r), shin_r)
val shout_r = (Cat(isSub(io.fn) & shin(xLen-1), shin).asSInt >> shamt)(xLen-1,0)
val shout_l = Reverse(shout_r)
val shout = Mux(io.fn === FN_SR || io.fn === FN_SRA || io.fn === FN_BEXT, shout_r, 0.U) |
            Mux(io.fn === FN_SL,                                          shout_l, 0.U)

val out = MuxLookup(io.fn, shift_logic_cond)(Seq(
  FN_ADD -> io.adder_out,
  FN_SUB -> io.adder_out
) ++ (if (coreParams.useZbb) Seq(
  FN_UNARY -> unary,
  FN_MAX -> maxmin_out,
  FN_MIN -> maxmin_out,
  FN_MAXU -> maxmin_out,
  FN_MINU -> maxmin_out,
  FN_ROL -> rotout,
  FN_ROR -> rotout,
) else Nil))

// TODO This should be a method on BitPat
private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width
// Pads BitPats that are safe to pad (no don't cares), errors otherwise
private def padBP(bp: BitPat, width: Int): BitPat = {
  if (bp.width == width) bp
  else {
    require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares")
    val diff = width - bp.width
    require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!")
    BitPat(0.U(diff.W)) ## bp
  }
}

def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = {
    val nElts = default.size
    require(mappingIn.forall(_._2.size == nElts),
      s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}"
    )

    val elementsGrouped = mappingIn.map(_._2).transpose
    val elementWidths = elementsGrouped.zip(default).map { case (elts, default) =>
      (default :: elts.toList).map(_.getWidth).max
    }
    val resultWidth = elementWidths.sum

    val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r }

    // All BitPats that correspond to a given element in the result must have the same width in the
    // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have
    // any don't cares. If there are don't cares, it is an error and the user needs to pad the
    // BitPat themselves
    val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
    val mappingInPadded = mappingIn.map { case (in, elts) =>
      in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
    }
    val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) })

    elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList
  }

when (RegNext(reset.asBool) && !reset.asBool) {
  s0_valid   := true.B
  s0_vpc     := io_reset_vector
  s0_ghist   := (0.U).asTypeOf(new GlobalHistory)
  s0_tsrc    := BSRC_C
}

icache.io.req.valid     := s0_valid
icache.io.req.bits.addr := s0_vpc

bpd.io.f0_req.valid      := s0_valid
bpd.io.f0_req.bits.pc    := s0_vpc
bpd.io.f0_req.bits.ghist := s0_ghist

when (s1_valid && !s1_tlb_miss) {
  // Stop fetching on fault
  s0_valid     := !(s1_tlb_resp.ae.inst || s1_tlb_resp.pf.inst)
  s0_tsrc      := BSRC_1
  s0_vpc       := f1_predicted_target
  s0_ghist     := f1_predicted_ghist
  s0_is_replay := false.B
}

when ((s2_valid && !icache.io.resp.valid) ||
      (s2_valid && icache.io.resp.valid && !f3_ready)) {
  s0_valid := (!s2_tlb_resp.ae.inst && !s2_tlb_resp.pf.inst) || s2_is_replay || s2_tlb_miss
  s0_vpc   := s2_vpc
  s0_is_replay := s2_valid && icache.io.resp.valid
  // When this is not a replay (it queried the BPDs, we should use f3 resp in the replaying s1)
  s0_s1_use_f3_bpd_resp := !s2_is_replay
  s0_ghist := s2_ghist
  s0_tsrc  := s2_tsrc
  f1_clear := true.B
} .elsewhen (s2_valid && f3_ready) {
  when (s1_valid && s1_vpc === f2_predicted_target && !f2_correct_f1_ghist) {
    // We trust our prediction of what the global history for the next branch should be
    s2_ghist := f2_predicted_ghist
  }
  when ((s1_valid && (s1_vpc =/= f2_predicted_target || f2_correct_f1_ghist)) || !s1_valid) {
    f1_clear := true.B

    s0_valid     := !((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay)
    s0_vpc       := f2_predicted_target
    s0_is_replay := false.B
    s0_ghist     := f2_predicted_ghist
    s2_fsrc      := BSRC_2
    s0_tsrc      := BSRC_2
  }
}
s0_replay_bpd_resp := f2_bpd_resp
s0_replay_resp := s2_tlb_resp
s0_replay_ppc  := s2_ppc

.elsewhen (( s2_valid &&  (s2_vpc =/= f3_predicted_target || f3_correct_f2_ghist)) ||
          (!s2_valid &&  s1_valid && (s1_vpc =/= f3_predicted_target || f3_correct_f1_ghist)) ||
          (!s2_valid && !s1_valid)) {
      f2_clear := true.B
      f1_clear := true.B

      s0_valid     := !(f3_fetch_bundle.xcpt_pf_if || f3_fetch_bundle.xcpt_ae_if)
      s0_vpc       := f3_predicted_target
      s0_is_replay := false.B
      s0_ghist     := f3_predicted_ghist
      s0_tsrc      := BSRC_3

      f3_fetch_bundle.fsrc := BSRC_3
    }

when (io.cpu.sfence.valid) {
  fb.io.clear := true.B
  f4_clear    := true.B
  f3_clear    := true.B
  f2_clear    := true.B
  f1_clear    := true.B

  s0_valid     := false.B
  s0_vpc       := io.cpu.sfence.bits.addr
  s0_is_replay := false.B
  s0_is_sfence := true.B

}.elsewhen (io.cpu.redirect_flush) {
  fb.io.clear := true.B
  f4_clear    := true.B
  f3_clear    := true.B
  f2_clear    := true.B
  f1_clear    := true.B

  f3_prev_is_half := false.B

  s0_valid     := io.cpu.redirect_val
  s0_vpc       := io.cpu.redirect_pc
  s0_ghist     := io.cpu.redirect_ghist
  s0_tsrc      := BSRC_C
  s0_is_replay := false.B

  ftq.io.redirect.valid := io.cpu.redirect_val
  ftq.io.redirect.bits  := io.cpu.redirect_ftq_idx
}

tlb.io.req.valid      := (s1_valid && !s1_is_replay && !f1_clear) || s1_is_sfence
...
  val s1_tlb_miss = !s1_is_replay && tlb.io.resp.miss
  val s1_tlb_resp = Mux(s1_is_replay, RegNext(s0_replay_resp), tlb.io.resp)
  val s1_ppc  = Mux(s1_is_replay, RegNext(s0_replay_ppc), tlb.io.resp.paddr)
  val s1_bpd_resp = bpd.io.resp.f1

  icache.io.s1_paddr := s1_ppc
  icache.io.s1_kill  := tlb.io.resp.miss || f1_clear

val f1_mask = fetchMask(s1_vpc)
val f1_redirects = (0 until fetchWidth) map { i =>
  s1_valid && f1_mask(i) && s1_bpd_resp.preds(i).predicted_pc.valid &&
  (s1_bpd_resp.preds(i).is_jal ||
    (s1_bpd_resp.preds(i).is_br && s1_bpd_resp.preds(i).taken))
}
val f1_redirect_idx = PriorityEncoder(f1_redirects)
val f1_do_redirect = f1_redirects.reduce(_||_) && useBPD.B
val f1_targs = s1_bpd_resp.preds.map(_.predicted_pc.bits)
val f1_predicted_target = Mux(f1_do_redirect,
                              f1_targs(f1_redirect_idx),
                              nextFetch(s1_vpc))

val f1_predicted_ghist = s1_ghist.update(
  s1_bpd_resp.preds.map(p => p.is_br && p.predicted_pc.valid).asUInt & f1_mask,
  s1_bpd_resp.preds(f1_redirect_idx).taken && f1_do_redirect,
  s1_bpd_resp.preds(f1_redirect_idx).is_br,
  f1_redirect_idx,
  f1_do_redirect,
  s1_vpc,
  false.B,
  false.B)

def isLastBankInBlock(addr: UInt) = {
  (nBanks == 2).B && addr(blockOffBits-1, log2Ceil(bankBytes)) === (numChunks-1).U
}
def mayNotBeDualBanked(addr: UInt) = {
  require(nBanks == 2)
  isLastBankInBlock(addr)
}
def fetchMask(addr: UInt) = {
  val idx = addr.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
  if (nBanks == 1) {
    ((1 << fetchWidth)-1).U << idx
  } else {
    val shamt = idx.extract(log2Ceil(fetchWidth)-2, 0)
    val end_mask = Mux(mayNotBeDualBanked(addr), Fill(fetchWidth/2, 1.U), Fill(fetchWidth, 1.U))
    ((1 << fetchWidth)-1).U << shamt & end_mask
  }
}

val f1_mask = fetchMask(s1_vpc)
val f1_redirects = (0 until fetchWidth) map { i =>
  s1_valid && f1_mask(i) && s1_bpd_resp.preds(i).predicted_pc.valid &&
  (s1_bpd_resp.preds(i).is_jal ||
    (s1_bpd_resp.preds(i).is_br && s1_bpd_resp.preds(i).taken))
}
val f1_redirect_idx = PriorityEncoder(f1_redirects)
val f1_do_redirect = f1_redirects.reduce(_||_) && useBPD.B
val f1_targs = s1_bpd_resp.preds.map(_.predicted_pc.bits)
val f1_predicted_target = Mux(f1_do_redirect,
                              f1_targs(f1_redirect_idx),
                              nextFetch(s1_vpc))
val f1_predicted_ghist = s1_ghist.update(
  s1_bpd_resp.preds.map(p => p.is_br && p.predicted_pc.valid).asUInt & f1_mask,
  s1_bpd_resp.preds(f1_redirect_idx).taken && f1_do_redirect,
  s1_bpd_resp.preds(f1_redirect_idx).is_br,
  f1_redirect_idx,
  f1_do_redirect,
  s1_vpc,
  false.B,
  false.B)

  def histories(bank: Int) = {
    if (nBanks == 1) {
      old_history
    } else {
      require(nBanks == 2)
      if (bank == 0) {
        old_history
      } else {
        Mux(new_saw_branch_taken                            , old_history << 1 | 1.U,
        Mux(new_saw_branch_not_taken                        , old_history << 1,
                                                              old_history))
      }
    }
  }  
def update(branches: UInt, cfi_taken: Bool, cfi_is_br: Bool, cfi_idx: UInt,
    cfi_valid: Bool, addr: UInt,
    cfi_is_call: Bool, cfi_is_ret: Bool): GlobalHistory = {
    val cfi_idx_fixed = cfi_idx(log2Ceil(fetchWidth)-1,0)
    val cfi_idx_oh = UIntToOH(cfi_idx_fixed)
    val new_history = Wire(new GlobalHistory)

    val not_taken_branches = branches & Mux(cfi_valid,
                                            MaskLower(cfi_idx_oh) & ~Mux(cfi_is_br && cfi_taken, cfi_idx_oh, 0.U(fetchWidth.W)),
                                            ~(0.U(fetchWidth.W)))

    if (nBanks == 1) {
      // In the single bank case every bank sees the history including the previous bank
      new_history := DontCare
      new_history.current_saw_branch_not_taken := false.B
      val saw_not_taken_branch = not_taken_branches =/= 0.U || current_saw_branch_not_taken
      new_history.old_history := Mux(cfi_is_br && cfi_taken && cfi_valid   , histories(0) << 1 | 1.U,
                                 Mux(saw_not_taken_branch                  , histories(0) << 1,
                                                                             histories(0)))
    } else {
      // In the two bank case every bank ignore the history added by the previous bank
      val base = histories(1)
      val cfi_in_bank_0 = cfi_valid && cfi_taken && cfi_idx_fixed < bankWidth.U
      val ignore_second_bank = cfi_in_bank_0 || mayNotBeDualBanked(addr)

      val first_bank_saw_not_taken = not_taken_branches(bankWidth-1,0) =/= 0.U || current_saw_branch_not_taken
      new_history.current_saw_branch_not_taken := false.B
      when (ignore_second_bank) {
        new_history.old_history := histories(1)
        new_history.new_saw_branch_not_taken := first_bank_saw_not_taken
        new_history.new_saw_branch_taken     := cfi_is_br && cfi_in_bank_0
      } .otherwise {
        new_history.old_history := Mux(cfi_is_br && cfi_in_bank_0                             , histories(1) << 1 | 1.U,
                                   Mux(first_bank_saw_not_taken                               , histories(1) << 1,
                                                                                                histories(1)))

        new_history.new_saw_branch_not_taken := not_taken_branches(fetchWidth-1,bankWidth) =/= 0.U
        new_history.new_saw_branch_taken     := cfi_valid && cfi_taken && cfi_is_br && !cfi_in_bank_0

      }
    }
    new_history.ras_idx := Mux(cfi_valid && cfi_is_call, WrapInc(ras_idx, nRasEntries),
                           Mux(cfi_valid && cfi_is_ret , WrapDec(ras_idx, nRasEntries), ras_idx))
    new_history
  }

val bank_data  = f3_data((b+1)*bankWidth*16-1, b*bankWidth*16)
val bank_mask  = Wire(Vec(bankWidth, Bool()))
val bank_insts = Wire(Vec(bankWidth, UInt(32.W)))

  for (b <- 0 until nBanks) {
.....

    for (w <- 0 until bankWidth) {
      val i = (b * bankWidth) + w
      bank_mask(w) := f3.io.deq.valid && f3_imemresp.mask(i) && valid && !redirect_found

    for (w <- 0 until bankWidth) {
...
      val brsigs = Wire(new BranchDecodeSignals)
      if (w == 0) {
        val inst0 = Cat(bank_data(15,0), f3_prev_half)
        val inst1 = bank_data(31,0)
...

        when (bank_prev_is_half) {
          bank_insts(w)                := inst0
...
          if (b > 0) {
            val inst0b     = Cat(bank_data(15,0), last_inst)
...
            when (f3_bank_mask(b-1)) {
              bank_insts(w)                := inst0b
              f3_fetch_bundle.insts(i)     := inst0b
              f3_fetch_bundle.exp_insts(i) := exp_inst0b
              brsigs                       := bpd_decoder0b.io.out
            }
          }
        } .otherwise {
          bank_insts(w)                := inst1
...
        }
        valid := true.B
      } else {
        val inst = Wire(UInt(32.W))
..
        val pc = f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U
...
        bank_insts(w)                := inst
...
        if (w == 1) {
          // Need special case since 0th instruction may carry over the wrap around
          inst  := bank_data(47,16)
          valid := bank_prev_is_half || !(bank_mask(0) && !isRVC(bank_insts(0)))
        } else if (w == bankWidth - 1) {
          inst  := Cat(0.U(16.W), bank_data(bankWidth*16-1,(bankWidth-1)*16))
          valid := !((bank_mask(w-1) && !isRVC(bank_insts(w-1))) ||
            !isRVC(inst))
        } else {
          inst  := bank_data(w*16+32-1,w*16)
          valid := !(bank_mask(w-1) && !isRVC(bank_insts(w-1)))
        }
      }
   last_inst = bank_insts(bankWidth-1)(15,0)
   ...
    }

val inst0 = Cat(bank_data(15,0), f3_prev_half)
val inst1 = bank_data(31,0)
val exp_inst0 = ExpandRVC(inst0)
val exp_inst1 = ExpandRVC(inst1)//inst0和1分别对应了RVI指令和未知的指令
val pc0 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U - 2.U)
val pc1 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U)

 for (b <- 0 until nBanks) {
...
    for (w <- 0 until bankWidth) {
...
      val brsigs = Wire(new BranchDecodeSignals)
      if (w == 0) {
        val inst0 = Cat(bank_data(15,0), f3_prev_half)
        val inst1 = bank_data(31,0)
        val exp_inst0 = ExpandRVC(inst0)
        val exp_inst1 = ExpandRVC(inst1)//inst0和1分别对应了RVI指令和未知的指令
        val pc0 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U - 2.U)
        val pc1 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U)
        val bpd_decoder0 = Module(new BranchDecode)
        bpd_decoder0.io.inst := exp_inst0
        bpd_decoder0.io.pc   := pc0
        val bpd_decoder1 = Module(new BranchDecode)
        bpd_decoder1.io.inst := exp_inst1
        bpd_decoder1.io.pc   := pc1

        when (bank_prev_is_half) {
          bank_insts(w)                := inst0
...
          bpu.io.pc                    := pc0
          brsigs                       := bpd_decoder0.io.out//指令不完整.且一定为32位,选择decode0的br信号
...
          if (b > 0) {
            val inst0b     = Cat(bank_data(15,0), last_inst)
            val exp_inst0b = ExpandRVC(inst0b)
            val bpd_decoder0b = Module(new BranchDecode)
            bpd_decoder0b.io.inst := exp_inst0b
            bpd_decoder0b.io.pc   := pc0

            when (f3_bank_mask(b-1)) {
...
              brsigs                       := bpd_decoder0b.io.out
            }
          }
        } .otherwise {
...
          bpu.io.pc                    := pc1
          brsigs                       := bpd_decoder1.io.out

        }
        valid := true.B
      } else {
        val inst = Wire(UInt(32.W))
        val exp_inst = ExpandRVC(inst)
        val pc = f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U
        val bpd_decoder = Module(new BranchDecode)
        bpd_decoder.io.inst := exp_inst
        bpd_decoder.io.pc   := pc
...
        bpu.io.pc                    := pc
        brsigs                       := bpd_decoder.io.out
...
      }

...
  }

      f3_targs (i) := Mux(brsigs.cfi_type === CFI_JALR,
        f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.bits,
        brsigs.target)

      // Flush BTB entries for JALs if we mispredict the target
      f3_btb_mispredicts(i) := (brsigs.cfi_type === CFI_JAL && valid &&
        f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.valid &&
        (f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.bits =/= brsigs.target)
      )


      f3_npc_plus4_mask(i) := (if (w == 0) {
        !f3_is_rvc(i) && !bank_prev_is_half
      } else {
        !f3_is_rvc(i)
      })
...  
  val f3_predicted_target = Mux(f3_redirects.reduce(_||_),
    Mux(f3_fetch_bundle.cfi_is_ret && useBPD.B && useRAS.B,
      ras.io.read_addr,
      f3_targs(PriorityEncoder(f3_redirects))
    ),
    nextFetch(f3_fetch_bundle.pc)
  )

val bpd_update_arbiter = Module(new Arbiter(new BranchPredictionUpdate, 2))
bpd_update_arbiter.io.in(0).valid := ftq.io.bpdupdate.valid
bpd_update_arbiter.io.in(0).bits  := ftq.io.bpdupdate.bits
assert(bpd_update_arbiter.io.in(0).ready)
bpd_update_arbiter.io.in(1) <> f4_btb_corrections.io.deq
bpd.io.update := bpd_update_arbiter.io.out
bpd_update_arbiter.io.out.ready := true.B

when (ftq.io.ras_update && enableRasTopRepair.B) {
  ras.io.write_valid := true.B
  ras.io.write_idx   := ftq.io.ras_update_idx
  ras.io.write_addr  := ftq.io.ras_update_pc
}

//下面是一次预测失败要经过的状态
//| br_info   |  b2     |reg(b2)        |             |             |  
//|   b1      |  red_val|mispred(false) |mispred(true)|mispred(false)|mispred(false)|          |____
//|           |         |repair(false)  |repair(false)|repair(true) |repair(true)  |          |    |一直运行直到修复完成
//                |                        repair_idx   repair_idx     repair_pc   |repair_idx| +__| 
//                |                        end_idx                     repair_idx  |          |
// (找到分支预测失败的ftq表项)                                          ()  
//

  when (io.redirect.valid) {
    bpd_update_mispredict := false.B
    bpd_update_repair     := false.B
  } .elsewhen (RegNext(io.brupdate.b2.mispredict)) {
    bpd_update_mispredict := true.B
    bpd_repair_idx        := RegNext(io.brupdate.b2.uop.ftq_idx)
    bpd_end_idx           := RegNext(enq_ptr)
  } .elsewhen (bpd_update_mispredict) {//
    bpd_update_mispredict := false.B
    bpd_update_repair     := true.B
    bpd_repair_idx        := WrapInc(bpd_repair_idx, num_entries)
  } .elsewhen (bpd_update_repair && RegNext(bpd_update_mispredict)) {
    bpd_repair_pc         := bpd_pc
    bpd_repair_idx        := WrapInc(bpd_repair_idx, num_entries)
  } .elsewhen (bpd_update_repair) {
    bpd_repair_idx        := WrapInc(bpd_repair_idx, num_entries)
    when (WrapInc(bpd_repair_idx, num_entries) === bpd_end_idx ||
      bpd_pc === bpd_repair_pc)  {
      bpd_update_repair := false.B
    }

  }

  when (io.redirect.valid) {//传入更新信息
    enq_ptr    := WrapInc(io.redirect.bits, num_entries)

    when (io.brupdate.b2.mispredict) {
    val new_cfi_idx = (io.brupdate.b2.uop.pc_lob ^
      Mux(redirect_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)
.......
    }

.......

  } .elsewhen (RegNext(io.redirect.valid)) {//信息传入完成
    prev_entry := RegNext(redirect_new_entry)
    prev_ghist := bpd_ghist
    prev_pc    := bpd_pc

    ram(RegNext(io.redirect.bits)) := RegNext(redirect_new_entry)
  }

for (i <- 0 until 2) {
  val idx = io.get_ftq_pc(i).ftq_idx
  val next_idx = WrapInc(idx, num_entries)
  val next_is_enq = (next_idx === enq_ptr) && io.enq.fire
  val next_pc = Mux(next_is_enq, io.enq.bits.pc, pcs(next_idx))
  val get_entry = ram(idx)
  val next_entry = ram(next_idx)
  io.get_ftq_pc(i).entry     := RegNext(get_entry)
  if (i == 1)
    io.get_ftq_pc(i).ghist   := ghist(1).read(idx, true.B)
  else
    io.get_ftq_pc(i).ghist   := DontCare
  io.get_ftq_pc(i).pc        := RegNext(pcs(idx))
  io.get_ftq_pc(i).next_pc   := RegNext(next_pc)
  io.get_ftq_pc(i).next_val  := RegNext(next_idx =/= enq_ptr || next_is_enq)
  io.get_ftq_pc(i).com_pc    := RegNext(pcs(Mux(io.deq.valid, io.deq.bits, deq_ptr)))
}

  def rotateLeft(in: UInt, k: Int) = {
    val n = in.getWidth
    Cat(in(n-k-1,0), in(n-1, n-k))
  }

  val might_hit_head = (1 until fetchWidth).map(k => VecInit(rotateLeft(tail, k).asBools.zipWithIndex.filter
    {case (e,i) => i % coreWidth == 0}.map {case (e,i) => e}).asUInt).map(tail => head & tail).reduce(_|_).orR
  val at_head = (VecInit(tail.asBools.zipWithIndex.filter {case (e,i) => i % coreWidth == 0}
    .map {case (e,i) => e}).asUInt & head).orR
  val do_enq = !(at_head && maybe_full || might_hit_head)

  io.enq.ready := do_enq
...  
val tail_collisions = VecInit((0 until numEntries).map(i =>
                          head(i/coreWidth) && (!maybe_full || (i % coreWidth != 0).B))).asUInt & tail
  val slot_will_hit_tail = (0 until numRows).map(i => tail_collisions((i+1)*coreWidth-1, i*coreWidth)).reduce(_|_)
  val will_hit_tail = slot_will_hit_tail.orR

  val do_deq = io.deq.ready && !will_hit_tail

  for (b <- 0 until nBanks) {
    for (w <- 0 until bankWidth) {
      val i = (b * bankWidth) + w
      val pc = (bankAlign(io.enq.bits.pc) + (i << 1).U)
      in_mask(i)                := io.enq.valid && io.enq.bits.mask(i)
...

      if (w == 0) {
        when (io.enq.bits.edge_inst(b)) {
          in_uops(i).debug_pc  := bankAlign(io.enq.bits.pc) + (b * bankBytes).U - 2.U
          in_uops(i).pc_lob    := bankAlign(io.enq.bits.pc) + (b * bankBytes).U
          in_uops(i).edge_inst := true.B
        }
      }
      in_uops(i).ftq_idx        := io.enq.bits.ftq_idx
      in_uops(i).inst           := io.enq.bits.exp_insts(i)
      in_uops(i).debug_inst     := io.enq.bits.insts(i)
      in_uops(i).is_rvc         := io.enq.bits.insts(i)(1,0) =/= 3.U
      in_uops(i).taken          := io.enq.bits.cfi_idx.bits === i.U && io.enq.bits.cfi_idx.valid

      in_uops(i).xcpt_pf_if     := io.enq.bits.xcpt_pf_if
      in_uops(i).xcpt_ae_if     := io.enq.bits.xcpt_ae_if
      in_uops(i).bp_debug_if    := io.enq.bits.bp_debug_if_oh(i)
      in_uops(i).bp_xcpt_if     := io.enq.bits.bp_xcpt_if_oh(i)

      in_uops(i).debug_fsrc     := io.enq.bits.fsrc
    }
  }

val enq_idxs = Wire(Vec(fetchWidth, UInt(numEntries.W)))

def inc(ptr: UInt) = {
  val n = ptr.getWidth
  Cat(ptr(n-2,0), ptr(n-1))
}

var enq_idx = tail
for (i <- 0 until fetchWidth) {
  enq_idxs(i) := enq_idx
  enq_idx = Mux(in_mask(i), inc(enq_idx), enq_idx)
}

for (i <- 0 until fetchWidth) {
  for (j <- 0 until numEntries) {
    when (do_enq && in_mask(i) && enq_idxs(i)(j)) {
      ram(j) := in_uops(i)
    }
  }
}

// Generate vec for dequeue read port.
for (i <- 0 until numEntries) {
  deq_vec(i/coreWidth)(i%coreWidth) := ram(i)
}

io.deq.bits.uops zip deq_valids           map {case (d,v) => d.valid := v}
io.deq.bits.uops zip Mux1H(head, deq_vec) map {case (d,q) => d.bits  := q}
io.deq.valid := deq_valids.reduce(_||_)

when (do_enq) {
  tail := enq_idx
  when (in_mask.reduce(_||_)) {
    maybe_full := true.B
  }
}

when (do_deq) {
  head := inc(head)
  maybe_full := false.B
}

when (io.clear) {
  head := 1.U
  tail := 1.U
  maybe_full := false.B
}

var metas = 0.U(1.W)
var meta_sz = 0
for (c <- components) {
  c.io.f0_valid  := io.f0_valid
  c.io.f0_pc     := io.f0_pc
  c.io.f0_mask   := io.f0_mask
  c.io.f1_ghist  := io.f1_ghist
  c.io.f1_lhist  := io.f1_lhist
  c.io.f3_fire   := io.f3_fire
  if (c.metaSz > 0) {
    metas = (metas << c.metaSz) | c.io.f3_meta(c.metaSz-1,0)
  }
  meta_sz = meta_sz + c.metaSz
}
require(meta_sz < bpdMaxMetaLength)
io.f3_meta := metas


var update_meta = io.update.bits.meta
for (c <- components.reverse) {
  c.io.update := io.update
  c.io.update.bits.meta := update_meta
  update_meta = update_meta >> c.metaSz
}

val bpdStr = new StringBuilder
bpdStr.append(BoomCoreStringPrefix("==Branch Predictor Memory Sizes==\n"))
val banked_predictors = (0 until nBanks) map ( b => {
  val m = Module(if (useBPD) new ComposedBranchPredictorBank else new NullBranchPredictorBank)
  for ((n, d, w) <- m.mems) {
    bpdStr.append(BoomCoreStringPrefix(f"bank$b $n: $d x $w = ${d * w / 8}"))
    total_memsize = total_memsize + d * w / 8
  }
  m
})
bpdStr.append(BoomCoreStringPrefix(f"Total bpd size: ${total_memsize / 1024} KB\n"))
override def toString: String = bpdStr.toString

val (components, resp) = getBPDComponents(io.resp_in(0), p)
io.resp := resp

....
    when (bank(io.f0_req.bits.pc) === 0.U) {
.......

      banked_predictors(0).io.f0_valid := io.f0_req.valid
      banked_predictors(0).io.f0_pc    := bankAlign(io.f0_req.bits.pc)
      banked_predictors(0).io.f0_mask  := fetchMask(io.f0_req.bits.pc)

      banked_predictors(1).io.f0_valid := io.f0_req.valid
      banked_predictors(1).io.f0_pc    := nextBank(io.f0_req.bits.pc)
      banked_predictors(1).io.f0_mask  := ~(0.U(bankWidth.W))
    } .otherwise {
....
      banked_predictors(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc)
      banked_predictors(0).io.f0_pc    := nextBank(io.f0_req.bits.pc)
      banked_predictors(0).io.f0_mask  := ~(0.U(bankWidth.W))
      banked_predictors(1).io.f0_valid := io.f0_req.valid
      banked_predictors(1).io.f0_pc    := bankAlign(io.f0_req.bits.pc)
      banked_predictors(1).io.f0_mask  := fetchMask(io.f0_req.bits.pc)
    }
    when (RegNext(bank(io.f0_req.bits.pc) === 0.U)) {
      banked_predictors(0).io.f1_ghist  := RegNext(io.f0_req.bits.ghist.histories(0))
      banked_predictors(1).io.f1_ghist  := RegNext(io.f0_req.bits.ghist.histories(1))
    } .otherwise {
      banked_predictors(0).io.f1_ghist  := RegNext(io.f0_req.bits.ghist.histories(1))
      banked_predictors(1).io.f1_ghist  := RegNext(io.f0_req.bits.ghist.histories(0))
    }

    val b0_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(0).io.f0_valid)))
    val b1_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(1).io.f0_valid)))
    banked_predictors(0).io.f3_fire := b0_fire
    banked_predictors(1).io.f3_fire := b1_fire

    banked_lhist_providers(0).io.f3_fire := b0_fire
    banked_lhist_providers(1).io.f3_fire := b1_fire
    // The branch prediction metadata is stored un-shuffled
    io.resp.f3.meta(0)    := banked_predictors(0).io.f3_meta
    io.resp.f3.meta(1)    := banked_predictors(1).io.f3_meta

    io.resp.f3.lhist(0)   := banked_lhist_providers(0).io.f3_lhist
    io.resp.f3.lhist(1)   := banked_lhist_providers(1).io.f3_lhist

...

    when (bank(io.resp.f3.pc) === 0.U) {
      for (i <- 0 until bankWidth) {
        io.resp.f3.preds(i)           := banked_predictors(0).io.resp.f3(i)
        io.resp.f3.preds(i+bankWidth) := banked_predictors(1).io.resp.f3(i)
      }
    } .otherwise {
      for (i <- 0 until bankWidth) {
        io.resp.f3.preds(i)           := banked_predictors(1).io.resp.f3(i)
        io.resp.f3.preds(i+bankWidth) := banked_predictors(0).io.resp.f3(i)
      }
    }

val io = IO(new Bundle {
  val f0_valid = Input(Bool())
  val f0_pc    = Input(UInt(vaddrBitsExtended.W))
  val f0_mask  = Input(UInt(bankWidth.W))
  // Local history not available until end of f1
  val f1_ghist = Input(UInt(globalHistoryLength.W))
  val f1_lhist = Input(UInt(localHistoryLength.W))

  val resp_in = Input(Vec(nInputs, new BranchPredictionBankResponse))
  val resp = Output(new BranchPredictionBankResponse)

  // Store the meta as a UInt, use width inference to figure out the shape
  val f3_meta = Output(UInt(bpdMaxMetaLength.W))

  val f3_fire = Input(Bool())

  val update = Input(Valid(new BranchPredictionBankUpdate))
})

case class BoomFAMicroBTBParams(
  nWays: Int = 16,
  offsetSz: Int = 13
)

  for (w <- 0 until bankWidth) {
    val entry_meta = meta(s1_hit_ways(w))(w)
    s1_resp(w).valid := s1_valid && s1_hits(w)
    s1_resp(w).bits  := (s1_pc.asSInt + (w << 1).S + btb(s1_hit_ways(w))(w).offset).asUInt
    s1_is_br(w)      := s1_resp(w).valid &&  entry_meta.is_br
    s1_is_jal(w)     := s1_resp(w).valid && !entry_meta.is_br
    s1_taken(w)      := !entry_meta.is_br || entry_meta.ctr(1)

    s1_meta.hits(w)     := s1_hits(w)
  }
...
  for (w <- 0 until bankWidth) {
    io.resp.f1(w).predicted_pc := s1_resp(w)
    io.resp.f1(w).is_br        := s1_is_br(w)
    io.resp.f1(w).is_jal       := s1_is_jal(w)
    io.resp.f1(w).taken        := s1_taken(w)

    io.resp.f2(w) := RegNext(io.resp.f1(w))
    io.resp.f3(w) := RegNext(io.resp.f2(w))
  }

val alloc_way = {
  val r_metas = Cat(VecInit(meta.map(e => VecInit(e.map(_.tag)))).asUInt, s1_idx(tagSz-1,0))
  val l = log2Ceil(nWays)
  val nChunks = (r_metas.getWidth + l - 1) / l
  val chunks = (0 until nChunks) map { i =>
    r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)
  }
  chunks.reduce(_^_)
}
s1_meta.write_way := Mux(s1_hits.reduce(_||_),
  PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),
  alloc_way)

// Write the BTB with the target
when (s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.cfi_idx.valid && s1_update.bits.is_commit_update) {
  btb(s1_update_write_way)(s1_update_cfi_idx).offset := new_offset_value
}

// Write the meta
for (w <- 0 until bankWidth) {
  when (s1_update.valid && s1_update.bits.is_commit_update &&
    (s1_update.bits.br_mask(w) ||
      (s1_update_cfi_idx === w.U && s1_update.bits.cfi_taken && s1_update.bits.cfi_idx.valid))) {
    val was_taken = (s1_update_cfi_idx === w.U && s1_update.bits.cfi_idx.valid &&
      (s1_update.bits.cfi_taken || s1_update.bits.cfi_is_jal))

    meta(s1_update_write_way)(w).is_br := s1_update.bits.br_mask(w)
    meta(s1_update_write_way)(w).tag   := s1_update_idx
    meta(s1_update_write_way)(w).ctr   := Mux(!s1_update_meta.hits(w),
      Mux(was_taken, 3.U, 0.U),
      bimWrite(meta(s1_update_write_way)(w).ctr, was_taken)
    )
  }
}

  val s2_req_rdata    = RegNext(data.read(s0_idx   , s0_valid))

  val s2_resp         = Wire(Vec(bankWidth, Bool()))

  for (w <- 0 until bankWidth) {

    s2_resp(w)        := s2_valid && s2_req_rdata(w)(1) && !doing_reset
    s2_meta.bims(w)   := s2_req_rdata(w)
  }
... 
 for (w <- 0 until bankWidth) {
    io.resp.f2(w).taken := s2_resp(w)
    io.resp.f3(w).taken := RegNext(io.resp.f2(w).taken)
  }

for (w <- 0 until bankWidth) {
  s1_update_wmask(w)         := false.B
  s1_update_wdata(w)         := DontCare

  val update_pc = s1_update.bits.pc + (w << 1).U

  when (s1_update.bits.br_mask(w) ||
    (s1_update.bits.cfi_idx.valid && s1_update.bits.cfi_idx.bits === w.U)) {
    val was_taken = (
      s1_update.bits.cfi_idx.valid &&
      (s1_update.bits.cfi_idx.bits === w.U) &&
      (
        (s1_update.bits.cfi_is_br && s1_update.bits.br_mask(w) && s1_update.bits.cfi_taken) ||
        s1_update.bits.cfi_is_jal
      )
    )
    val old_bim_value = Mux(wrbypass_hit, wrbypass(wrbypass_hit_idx)(w), s1_update_meta.bims(w))

    s1_update_wmask(w)     := true.B

    s1_update_wdata(w)     := bimWrite(old_bim_value, was_taken)
  }


}

when (doing_reset || (s1_update.valid && s1_update.bits.is_commit_update)) {
  data.write(
    Mux(doing_reset, reset_idx, s1_update_index),
    Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 2.U }), s1_update_wdata),
    Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmask.asUInt).asBools
  )
}

class BoomRAS(implicit p: Parameters) extends BoomModule()(p)
{
  val io = IO(new Bundle {
    val read_idx   = Input(UInt(log2Ceil(nRasEntries).W))
    val read_addr  = Output(UInt(vaddrBitsExtended.W))

    val write_valid = Input(Bool())
    val write_idx   = Input(UInt(log2Ceil(nRasEntries).W))
    val write_addr  = Input(UInt(vaddrBitsExtended.W))
  })
  val ras = Reg(Vec(nRasEntries, UInt(vaddrBitsExtended.W)))

  io.read_addr := Mux(RegNext(io.write_valid && io.write_idx === io.read_idx),
    RegNext(io.write_addr),
    RegNext(ras(io.read_idx)))

  when (io.write_valid) {
    ras(io.write_idx) := io.write_addr
  }
}

case class BoomTageParams(
  //                                           nSets, histLen, tagSz
  tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq((  128,       2,     7),
                                              (  128,       4,     7),
                                              (  256,       8,     8),
                                              (  256,      16,     8),
                                              (  128,      32,     9),
                                              (  128,      64,     9)),
  uBitPeriod: Int = 2048
)

table.write(
  Mux(doing_reset, reset_idx                                          , update_idx),
  Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
  Mux(doing_reset, ~(0.U(bankWidth.W))                                , io.update_mask.asUInt).asBools
)

  val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
  val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
  val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
  val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
...  
hi_us.write(
    Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
    Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
    Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
  )

var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
//
for (i <- 0 until tageNTables) {
  val hit = f3_resps(i)(w).valid
  val ctr = f3_resps(i)(w).bits.ctr
  when (hit) {
    io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))//预测可能不准
    final_altpred       := altpred
  }

  provided = provided || hit
  provider = Mux(hit, i.U, provider)
  altpred  = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits  := provider
f3_meta.alt_differs(w)    := final_altpred =/= io.resp.f3(w).taken//有预测未命中的项
f3_meta.provider_u(w)     := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w)   := f3_resps(provider)(w).bits.ctr

val allocatable_slots = (
  VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
  ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)//如果u=0的个数大于1,使用LSFR选择,概率是历史长的大于历史短的

val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
  masked_entry,
  first_entry)

f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits  := alloc_entry

val update_was_taken = (s1_update.bits.cfi_idx.valid &&
                        (s1_update.bits.cfi_idx.bits === w.U) &&
                        s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
  when (s1_update_meta.provider(w).valid) {
    val provider = s1_update_meta.provider(w).bits

    s1_update_mask(provider)(w) := true.B
    s1_update_u_mask(provider)(w) := true.B

    val new_u = inc_u(s1_update_meta.provider_u(w),
                      s1_update_meta.alt_differs(w),
                      s1_update_mispredict_mask(w))
    s1_update_u      (provider)(w) := new_u
    s1_update_taken  (provider)(w) := update_was_taken
    s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
    s1_update_alloc  (provider)(w) := false.B

  }
}

when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
  val idx = s1_update.bits.cfi_idx.bits
  val allocate = s1_update_meta.allocate(idx)
  when (allocate.valid) {
    s1_update_mask (allocate.bits)(idx) := true.B
    s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
    s1_update_alloc(allocate.bits)(idx) := true.B

    s1_update_u_mask(allocate.bits)(idx) := true.B
    s1_update_u     (allocate.bits)(idx) := 0.U

  } .otherwise {
    val provider = s1_update_meta.provider(idx)
    val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)

    for (i <- 0 until tageNTables) {
      when (decr_mask(i)) {
        s1_update_u_mask(i)(idx) := true.B
        s1_update_u     (i)(idx) := 0.U
      }
    }
  }

}